For IP block-to-chip verification, enhancements include:



- New Trident engine in the Incisive Formal Verifier and the Incisive Enterprise Verifier, which improves formal analysis performance up to 20X

- New constraint engine in the Incisive Enterprise Simulator that speeds UVM and SystemVerilog testbench simulation, and simulation acceleration with the Palladium platform by up to 10X

- New SystemVerilog support in Incisive Debug Analyzer plus unique UVM debug capabilities and optimized probing in the SimVision debug environment inside Incisive Enterprise Simulator that reduces database size up to 10X

- New IEEE 1647 e unit testing without simulation, reducing debug time for testbench code by 30%



For SoC verification, enhancements include:



- Comprehensive x-propagation support in the Incisive Enterprise Simulator and the Incisive Enterprise Verifier to speed SoC reset and low-power simulations up to 5X

- New support for SystemVerilog IEEE 1800-2012 real number modeling in the Incisive Digital Mixed Signal option for faster mixed-signal simulation over 100X.



The complete list of key performance enhancements and productivity features can be found

About Cadence



Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.



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